1. Field of the Invention
This invention is related to the fields of packet processing and coherency.
2. Description of the Related Art
With the continued expansion of networks, networked systems (e.g. local area networks (LANs), wide area networks (WANs), the Internet, etc.), and emerging storage subsystem technologies such as network attached storage (NAS) and storage area network (SAN), packet processing is an increasingly important function for a variety of systems. The amount of packet processing to be performed may be increasing due to the increased amount of packet traffic, as well as the more sophisticated packet processing that is being attempted on each packet (e.g. processing at deeper layers of the packet).
In the past, packet processing circuitry was often implemented via fixed-function (non-programmable) devices. As packet interfaces, packet content, and packet standards evolved, the fixed-function devices would be redesigned to handle the changes. More recently, network processing units (NPUs) have been implemented to provide programmable packet processing solutions. However, NPUs have generally not provided robust scalability to multiple NPUs, and thus NPUs may have to be replaced when the processing power of the NPUs is no longer sufficient to handle the desired packet processing.